Field of Use
This invention relates to timing circuits and, more particularly, to timing circuits constructed from delay lines.
Generally, in digital computer systems, the subsystems and/or digital logic circuits are interconnected through transmission line buses such as coaxial cable, microstrip transmission lines or the line. Each of the subsystems include separate timing circuits which establish the overall timing for the subsystem and are used to generate the necessary control signals for gaining access to the bus.
An example of such a subsystem is disclosed in the copending patent application entitled "A Dynamic Memory System which Includes Apparatus for Performing Refresh Operations in Parallel with Normal Memory Operations" bearing Ser. No. 926,480, filed on July 20, 1978 and now U.S. Pat. No. 4,185,323 and assigned to the same assignee as named herein. In order to provide the desired sequences of signals for operation of the memory subsystem, it is necessary to connect a pair of delay line circuits in series.
It has been found that while the delay lines are constructed to provide equal increments of delay and the same characteristic impedance, cascading or connecting them in series gives rise to a mismatch condition which tends to make the operation of the timing generator circuit less reliable. One approach is not to cascade the delay lines but to include additional driver buffer circuits to eliminate any mismatch. This results in added circuit complexity and cost in addition to altering the delay time of the lines.
Accordingly, it is a primary object of the present invention to provide an improved timing circuit.
It is a further object of the present invention to provide a delay line timing circuit which includes a minimum number of additional circuits for ensuring reliable operation.